1. Technical Field
The present invention generally relates to performance enhancement in phase-locked loop (PLL) circuits, and more particularly to automatic static phase error and jitter compensation in PLL circuits.
2. Description of the Related Art
As integrated circuit technology advances, it becomes more and more difficult to predict and to control, within tight tolerances, the behavior of integrated circuit elements. These integrated circuit elements may include transistors as well as passive elements such as resistors and capacitors. In addition, non-idealities in the performance of key circuit elements such as current mirrors also tend become more and more pronounced with each ensuing technology generation.
As the variability in individual devices grows and as device performance departs further and further from the ideal, it becomes increasingly important to identify efficient ways to compensate for process, voltage, temperature, and aging effects in integrated circuits.
One broad approach to addressing these problems is to convert aspects of circuits that are implemented in an open loop, and correct them by designs with blocks implemented using closed loop feedback techniques. Such a transition needs a sensor that can measure performance of the circuit block against a specification, an actuator that can effect a change in the performance of the circuit block, and a control loop that ensures that the actuator is controlled in such a way that circuit block performance is brought closer to the target when the loop is active.
The problems associated with advancing integrated circuit technology strongly affect analog circuits, and particularly phase-locked loop (PLL) circuits. One key metric of PLL performance is static phase error. The static phase error is a long-term value of a time difference between an arrival time of an input reference clock and a PLL feedback clock at the input of the PLL's phase and frequency detector block. While it is typically desirable to minimize this quantity, there may also be cases in which it is desirable to drive this quantity to a known, pre-set value.
Another key metric of PLL performance is its output jitter. Again, while it is typically desirable to minimize this quantity, there may also be cases in which it is desirable to drive characteristics of this quantity to a known value, as in multi-PLL systems where the matching of jitter characteristics is important.
Static phase error minimization described in the art has typically relied upon open-loop techniques that improve the underlying baseline performance of PLL sub-circuits. Such approaches do not treat static phase error directly as a quantity to be measured and then compensated. Furthermore, these techniques do not allow for the achievement of a target non-minimum static phase error. Similarly, approaches to jitter minimization have focused on open-loop techniques that improve the underlying baseline jitter behavior of the overall PLL, Such approaches do not enable optimization of the PLL as a function of the noise content of the input reference signal, for example.